1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and in particular to a semiconductor device having a semiconductor substrate with reduced damage a gate electrode with high dimensional controllability and a method of manufacturing the same.
2. Description of the Background Art
One example of a conventional method of manufacturing a semiconductor device will now be described with reference to the figures. Referring to FIG. 26, a gate oxide film 105 is formed on a semiconductor substrate 101 by thermal oxidation or the like. A polysilicon film 107 is formed on gate oxide film 105 by chemical vapor deposition (CVD) or the like. A photoresist pattern 109 having a predetermined width is formed on polysilicon film 107.
Referring now to FIG. 27, photoresist pattern 109 is used as a mask to anisotropically etch polysilicon film 107. At the initial stage of the anisotropic etching, polysilicon film 107 remains on the entire surface of semiconductor substrate 101. Thus, the polysilicon film during plasma process is equipotential at all portions.
As the anisotropic etching proceeds, however, the polysilicon film remains in the shape of a mesa on semiconductor substrate 101. The remaining polysilicon film is charged to the potential which is determined by the sheath between the plasma and semiconductor substrate 101. Thus, electrical stress is applied to gate oxide film 105 in accordance with the difference between the potential of the polysilicon film and the potential of the semiconductor substrate.
Referring now to FIG. 28, gate oxide film 105 can be damaged in over-etching particularly at the portion indicated by A in the figure. More specifically, referring to FIG. 29, gate oxide film 105 is damaged in the vicinity of the portion immediately under a side surface of a gate electrode 107a. Then, gate electrode 107a is used as a mask and ion-implantation is performed on semiconductor substrate 101 to form a pair of source/drain regions (not shown). An MOS transistor including a gate electrode and source/drain regions is thus formed. In an MOS transistor thus formed, threshold voltage varies and the breakdown voltage of the gate oxide film is decreased, resulting in deterioration of its reliability.
A method of manufacturing a semiconductor device disclosed in Japanese Patent Laying-Open No. 6-151834 will now be described as a first technique to solve such problems with reference to the Figures.
Referring first to FIG. 30, a gate oxide film 202 of approximately 80 .ANG. is formed on a p-type silicon substrate 201 on which a first thin, polycrystalline silicon film 203 of approximately 200 .ANG. is formed by low pressure CVD. It is then left in the atmosphere for one hour. Then, low pressure CVD is employed to form a second thin, polycrystalline silicon film 204 of approximately 3000 .ANG..
Present between the first thin, polycrystalline silicon film 203 and the second thin, polycrystalline silicon film 204 is native oxide 209 of approximately 10 .ANG. which adheres while the first thin, polycrystalline silicon film 203 is left in the atmosphere.
Referring now to FIG. 31, photolithography is employed to selectively form a photoresist 208 at the portion at which a gate electrode is to be formed. In this state, reactive ion etching is performed to selectively remove that portion of the second thin, polycrystalline silicon film 204 which is not covered with photoresist 208.
After the second thin, polycrystalline silicon film 204 has been removed, native oxide film 209 will be etched. Consequently, the end point of etching in the reactive ion etching system is detected, and the first thin, polycrystalline silicon film 203 is exposed or native oxide film 209 partially remains on the surface.
Referring now to FIG. 32, a heat treatment is performed in dry O.sub.2 ambient to completely alter that portion of the first thin, polycrystalline silicon film 203 which is not located immediately under the gate electrode into an oxide film 205. Arsenic ions 206 are ion-implanted to form an ion-implantation layer 207.
Referring now to FIG. 33, a heat treatment is performed in N.sub.2 ambient to form a pair of n-type source/drain diffusion layers 207a and 207b. An MOS transistor is thus formed which includes an electrode having the first thin, polycrystalline silicon film 203 and the second thin, polycrystalline silicon film 204, and source/drain diffusion layers 207a and 207b.
In this manufacturing method, the first thin, polycrystalline silicon film 203 covers gate oxide film 202 on p-type silicon substrate 201 in forming a gate electrode by anisotropic etching. Thus, damaging from the anisotropic etching to gate oxide 202 is suppressed.
A method of manufacturing a gate electrode of a semiconductor device disclosed in Japanese Patent Laying-Open No. 3-136277 will now be described as a second technique to solve the aforementioned problems with reference to the Figures.
Referring first to FIG. 34, a gate oxide film 302 of approximately 150 .ANG. is formed on a silicon substrate 301. Phosphorus doped, polycrystalline silicon of approximately 2000 .ANG. is deposited as a material for a gate electrode on gate oxide film 302 to form a first polycrystalline silicon film 303. After native oxide 304 is formed on the upper surface of the first thin, polycrystalline silicon film 303, phosphorus doped, polycrystalline silicon of approximately 5000 .ANG. is deposited to form a second polycrystalline silicon film 305.
Referring now to FIG. 35, photolithography for patterning a gate electrode is applied to the second polycrystalline silicon film 305 to anisotropically etch the second polycrystalline silicon 305 until native oxide 304 is exposed.
Native oxide 304 acts as a stopper layer for stopping the etching, and the second polycrystalline silicon film 305 other than the pattern of the gate electrode and a portion of native oxide 304 are removed.
Referring now to FIG. 36, an antioxidation film 306 of 3000 .ANG. formed of silicon nitride film or the like are formed on the entire surface of the first and second polycrystalline silicon films 303 and 305.
Referring then to FIG. 37, antioxidation film 306 is anisotropically etched to leave antioxidation film 306 only on a side surface of the second polycrystalline silicon film 305.
Referring then to FIG. 38, the polycrystalline silicon is wet-oxidized (850.degree. C., one hour) and a polycrystalline silicon oxide film 307 is formed in the entire region of the first polycrystalline silicon film 303 other than the electrode pattern. A polycrystalline silicon oxide film 308 is also formed in an upper portion of the second polycrystalline silicon film 305.
Polycrystalline silicon oxide film 307 extends inwards by a distance E from an edge located under the pattern of the gate electrode. Distance E is adjusted by changing the oxidation time of the wet oxidation.
Referring then to FIG. 39, anisotropic etching is performed to remove antioxidation film 306 on the side surface of the second polycrystalline silicon film 305, and polycrystalline silicon oxide film 307 other than the pattern of the gate electrode, and polycrystalline silicon oxide film 308 on the pattern of the gate electrode. A gate electrode 309 is thus formed.
For gate electrode 309 form according to the aforementioned manufacturing method, polycrystalline silicon oxide film 307 extending into the first polycrystalline silicon film 303 remains on gate oxide film 302 exactly under a side surface of the gate electrode. Thus, electric field concentration exactly under the side surface of the gate electrode is significantly relaxed, and damage from the electric field concentration to gate oxide film 302 is suppressed.
However, each of the conventional techniques has the problems described below.
For the first technique, the first thin, polycrystalline silicon film 203 and the second thin, polycrystalline silicon film 204 exposed in FIG. 31 is thermally oxidized in the step shown in FIG. 32. The amount of oxidation depends on oxidation time and thus the amount of the first thin, polycrystalline silicon film 204 oxidized is almost equal to that of the second thin, polycrystalline silicon film 205 oxidized. It is thus difficult to achieve further precise control of the dimensions of the gate electrode, such as change of effective gate length and the height of the gate electrode.
For the second technique, the second polycrystalline silicon film 305 and the exposed first polycrystalline silicon film 303 shown in FIG. 37 are oxidized in water vapor ambient in the step shown in FIG. 38. In this example also, as is with the first technique, further precise control of the dimension of the gate electrode, such as change in dimension E shown in FIG. 38 and the height of the gate electrode, is difficult to achieve.
In the first technique, the entire surface of oxide film 205 can further be anisotropically etched after the step shown in FIG. 33 to form a sidewall on both sides of the first and second thin, polycrystalline silicon films 203 and 204. In the second technique also, a silicon nitride film can be formed on silicon substrate 301 after the step shown in FIG. 39 to cover the second polycrystalline silicon film 305 and the silicon nitride film can be anisotropically etched to form a sidewall on both sides of the first and second polycrystalline silicon films 303 and 305.
In these examples, the anisotropic etching can damage p-type silicon substrate 201 or silicon substrate 301 in the vicinity of its surface, or the silicon substrate can be etched.
Thus, precise control of the dimensions of a gate electrode can be difficult to achieve and a semiconductor substrate can be damaged by anisotropic etching in forming a sidewall on the gate electrode in the conventional methods of manufacturing semiconductor devices.